1. Technical Field
The present invention relates to ferroelectric memory devices (ferroelectric memories) that use ferroelectric capacitors, and electronic apparatuses equipped with the same, and more particularly, to improvement of the technology for generating reference potentials to be used for data judgment.
2. Related Art
Ferroelectric memory devices (FeRAMs) have a non-volatile property, and are characterized by operation capability equal to that of conventional DRAMs or the like, and therefore have been drawing attention in recent years. When a 1T1C type in which one ferroelectric capacitor and one transistor are combined is used as a memory cell of a ferroelectric memory device, a reference potential is required as a criterion when reading data stored in the memory cell and judging the content of the data (“0” or “1”). As a method to generate the reference potential, a method that uses a constant potential generation circuit, a method that uses a reference cell (dummy cell) and the like are known.
A conventional example of the technology for generating a reference potential by using a dummy cell is described in, for example, Japanese Laid-open Patent Application HEI 10-125076. In the ferroelectric memory described in this document, at the time of readout operation, a dummy capacitor having a predetermined capacitance is connected with a non-inverted bit line to be connected with a selected ferroelectric memory cell, and the value of capacitance thereof is set to be greater than that of an inverted bit line to be connected with a corresponding dummy cell, thereby optimizing the reference potential (voltage level) obtained by the dummy cell.
However, in the conventional technology described above, a dummy capacitor circuit for connecting a dummy capacitor to a non-inverted bit line at a desired timing is required to be added, which is inconvenient because this would likely result in an increase in the device area.
Therefore, it is an object of the present invention to provide a technology for a ferroelectric memory device that generates a reference potential by using a dummy cell, whereby its control at the time of readout can be readily performed, and an increase in the device area can be suppressed.